VLSI & Digital Circuit Design
An introductory project track covering Verilog HDL, RTL synthesis, timing analysis, and ASIC backend concepts using open-source EDA tools.
A real sequence, not a playlist
Six numbered weeks. Every week ends in a deliverable a reviewer actually checks — plan roughly twenty focused hours per week.
Course workspace: 23 lessons · 11 reads · 6 checkpoints · 6 reviewed builds
- 01~20h effort
Week 1 · Digital Logic & Verilog Foundations
- —Combinational and sequential design discipline
- —Synthesizable Verilog style and lint-clean code
- —Simulation with Icarus Verilog and GTKWave
Deliverable: Lint-clean RTL block library + waveforms
- 02~20h effort
Week 2 · FSMs, Pipelining & Memory
- —Finite-state machines: Mealy vs. Moore in practice
- —Pipelined datapaths and hazard handling
- —SRAM interfaces and memory-mapped peripherals
Deliverable: Pipelined peripheral with timing diagram
- 03~20h effort
Week 3 · Verification Methodics
- —Testbench architecture and self-checking tests
- —Functional coverage and corner-case hunting
- —Regression discipline and failure triage
Deliverable: Coverage report clearing the review gate
- 04~20h effort
Week 4 · Synthesis & Static Timing Analysis
- —Yosys synthesis flow and constraint files
- —Setup/hold analysis with OpenSTA
- —Closing timing: pipelining vs. constraints
Deliverable: Synthesized netlist meeting timing
- 05~20h effort
Week 5 · Backend: Floorplan to GDS Thinking
- —Floorplanning, placement, and clock-tree concepts
- —Power grid and IR-drop awareness
- —DRC/LVS literacy with open PDKs
Deliverable: Floorplan notes and sign-off checklist
- 06~20h effort
Week 6 · Final Project Review
- —Design reflection on RTL and timing decisions
- —Completion review against the published rubric
- —Training-completion record when requirements are met
Deliverable: Final project submission
Checked by named reviewers
Reviewers are named at cohort start and published with the batch. They check every submission against the rubric — passing names appear on the certificate.
- Every submission checked against a published academic and technical rubric
- One fair remediation attempt if a deliverable falls short of acceptance threshold
- No certificate without passing code checks — payment never substitutes genuine review
- Cryptographic verification QR permanently linked to your individual submission records
Where ECE / EE students take this track
Matched by branch against the BEU college directory — not an affiliation claim. Academic credit is decided by each college's T&P cell, so ask your HoD to review the syllabus before you enrol.